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Global Mixed-mode Technology Inc.
G571
Single-Slot PCMCIA/CardBus Power Controllers
Features
Fully Integrated VCC and VPP Switching for Single-Slot PC CardTM Interface Low rDS(on) (180-m 5V VCC Switch and 3.3V VCC Switch) Compatible With Controllers From Cirrus, Ricoh, O2Micro, Intel, and Texas Instruments 3.3V Low-Voltage Mode Meets PC Card Standards 12V Supply Can Be Disabled Except During 12V Flash Programming Short Circuit and Thermal Protection Space-Saving 16 Pin SSOP Compatible With 3.3V, 5V, and 12V PC Cards Break-Before-Make Switching
Description
The G571 PC Card power-interface switch provides an integrated power-management solution for a single PC Cards. All of the discrete power MOSFETs, a logic section, current limiting, and thermal protection for PC Card control are combined on a single integrated circuit. The circuit allows the distribution of 3.3V, 5V, and/or 12V card power, and is compatible with many PCMCIA controllers. The current-limiting feature eliminates the need for fuses, which reduces component count and improves reliability. Current-limit reporting can help the user isolate a system fault to the PC Card. The G571 features a 3.3V low voltage mode that allows for 3.3V switching without the need for 5V. Bias power can be derived from either the 3.3V or 5V inputs. This facilitates low-power system designs such as sleep mode and pager mode where only 3.3V is available. End equipment for the G571 includes notebook computers, desktop computers, personal digital assistants (PDAs), digital cameras and bar-code scanners.
Application
Notebook PC Electronic Dictionary Personal Digital Assistance Digital still Camera
Ordering Information
PART NUMBER
G571S1
TEMP. RANGE
-40C to +85C
PACKAGE
16-SSOP
Pin Configuration
G571
VCCD0 VCCD1 3.3V 3.3V 5V 5V GND OC 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 SHDN VPPD0 VPPD1 AVCC AVCC AVCC AVPP 12V
16Pin SSOP
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Global Mixed-mode Technology Inc.
Typical PC-card Power-distribution application
AVCC AVCC AVCC 0.1F VCC1 VCC2 VPP1 AVPP 12V 5V 0.1F 1F 12V 5V 5V VCCD0 3.3V 0.1F 1F 3.3V 3.3V VCCD1 VPPD0 VPPD1 OC SHDN To CPU 0.1F VPP2
G571
PC Card Connector
G571
PCMCIA Controller
VCC_EN0 VCC_EN1 VPP_EN0 VPP_EN1 CS
GND
Shutdown Signal From CPU
Terminal Functions
TERMINAL NAME
3.3V 5V 12V AVCC AVPP GND
OC SHDN VCCD0
NO.
3,4 5,6 9 11,12,13 10 7 8 16 1 2 15 14
I/O
I I I O O O I I I I I
DESCRIPTION
3.3V VCC input for card power and/or chip power if 5V is not present 5V VCC input for card power and/or chip power 12V VPP input card power Switched output that delivers 0V,3.3V,5V, or high impedance to card Switched output that delivers 0V,3.3V,5V,12V or high impedance to card Ground Logic-level overcurrent reporting output that goes low when an overcurrent condition exists Logic input that shuts down the G571 and sets all power outputs to high-impedance state Logic input that controls voltage of AVCC(see control-logic table) Logic input that controls voltage of AVCC(see control-logic table) Logic input that controls voltage of AVPP(see control-logic table) Logic input that controls voltage of AVPP(see control-logic table)
VCCD1
VPPD0 VPPD1
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Global Mixed-mode Technology Inc.
Absolute Maximum Ratings Over Operating Free-Air Temperature (unless other-wise noted)*
Input voltage range for card power: VI(5V) ............................................................-0.3V to 7V VI(3.3V) ........................................................ -0.3V to 7V VI(12V) .........................................................-0.3V to 14V Logic input voltage.........................................-0.3V to 7V Output current (each card):IO (VCC)..........internally limited IO(VPP)............internally limited
G571
Operating virtual junction temperature range, TJ. ........................................................-40C to 150C Operating free-air temperature range,.TA .....................................................................................-40C to 85C Storage temperature range, TSTG .......................................................-55C to 150C Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds..................................................260C
*Stresses beyond those listed under "absolute maximum
ratings"may cause permanent damage to the device. These are stress
rating only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions"is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Recommended Operating Conditions
MIN
VI(5V) Input voltage, VI VI(3.3V) VI(12V) IO(AVCC) Output current IO(AVPP) Operating virtual junction temperature, TJ 0 0 0
MAX
5.25 5.25 13.5 1.0 150 125
UNIT
V V V A mA
-40
C
Electrical Characteristics (TA=25C)
Power Switch PARAMETER
5V to AVCC 3.3V to AVCC 3.3V to AVCC 5V to AVPP 3.3V to AVPP 12V to AVPP
TEST CONDITIONS*
VI(5V) = 5V VI(5V) = 5V, VI(3.3V) =3.3V VI(5V) = 0V, VI(3.3V) =3.3V TJ = 25C TJ = 25C TJ = 25C IPP at 10mA
MIN TYP MAX UNIT
130 130 130 180 180 180 6 6 6 0.8 0.8 10 10 150 150 3 2.2 400 m
Switch resistance
V V A
VO(AVPP) Clamp low voltage VO(AVCC) Clamp low voltage IIKG Leakage current I PP
ICC at 10mA high-impedance State TA = 25C TA = 25C VO(AVCC)=5V,VO(AVPP)=12V VO(AVCC)=3.3V,VO(AVPP)= 12V VO(AVCC)=VO(AVPP) = Hi-Z output powered into a short to GND
1 1 75 75 1 0.8 120
II IOS
Input current Short-circuit Outputcurrent Limit
I CC high-impedance State VI(5V) = 5V VI(5V) = 0V, VI(3.3V) = 3.3V Shutdown mode IO(AVCC) IO(AVPP)
A A mA
*Pulse-testing techniques maintain junction temperature close to ambient temperatures; thermal effects must be taken into account separately.
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Global Mixed-mode Technology Inc.
Logic Section PARAMETER
Logic input current Logic input high level Logic input low level Logic output high level Logic output low level VI(5V) = 5V, IO=1mA VI(5V)=0V,IO= 1mA,VI(3.3V)= 3.3V IO = 1mA 2
G571
MIN MAX
1 0.8 VI(5V) - 0.4 VI(3.3V) - 0.4 0.4
TEST CONDITION*
UNIT
A V V V V
*Pulse-testing techniques maintain junction temperature close to ambient temperatures; thermal effects must be taken into account separately.
Switching Characteristics ** PARAMETER
tr tf Rise times, output Fall times, output VO (AVCC) VO (AVPP) VO (AVCC) VO (AVPP) VI(VPPD0) to VO(AVPP) tpd Propagation delay (see Figure 1) VI( VCCD1 ) to VO(AVCC) (3.3V) VI( VCCD0 ) to VO(AVCC) (5V)
**Switching Characteristics are with CL = 147F. Refer to Parameter Measurement Information
TEST CONDITION
MIN
TYP
2.6 10 7.5 38
MAX
UNIT
ms
ton toff ton toff ton toff
14 44 3.2 17 4.4 20 ms
Parameter Measurement Information
AVPP CL AVCC CL
LOAD CIRCUIT VI(VPPD0) (VI(VPPD1)=0V) toff ton VI(12V) VO(AVPP) 90% 10% VOLTAGE WAVEFORMS GND VO(AVCC) VDD 50% 50% GND VI(VCCD1) (VI(VCCD0)=VDD)
LOAD CIRCUIT VDD 50% 50% toff ton VI(3.3V) 90% 10% VOLTAGE WAVEFORMS GND GND
Figure 1. Test Circuits and Voltage Waveforms Table of Timing Diagrams FIGURE
AVCC Propagation Delay and Rise Time With 1F Load, 3.3V Switch AVCC Propagation Delay and Fall Time With 1F Load, 3.3V Switch AVCC Propagation Delay and Rise Time With 147F Load, 3.3V Switch AVCC Propagation Delay and Fall Time With 147F Load, 3.3V Switch AVCC Propagation Delay and Rise Time With 1F Load, 5V Switch AVCC Propagation Delay and Fall Time With 1F Load, 5V Switch AVCC Propagation Delay and Rise Time With 147F Load, 5V Switch AVCC Propagation Delay and Fall Time With 147F Load, 5V Switch AVPP Propagation Delay and Rise Time With 1F Load, 12V Switch AVPP Propagation Delay and Fall Time With 1F Load, 12V Switch AVPP Propagation Delay and Rise Time With 147F Load, 12V Switch AVPP Propagation Delay and Fall Time With 147F Load, 12V Switch 2 3 4 5 6 7 8 9 10 11 12 13
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Global Mixed-mode Technology Inc.
Parameter Measurement Information
G571
V C C D 0 = 3.3 V
V C C D 0 = 3 .3 V
VCCD1
VCCD1
AV C C
AV C C
Figure 2. AVCC Propagation Delay and Rise Time With 1F Load, 3.3V Switch
Figure 3. AVCC Propagation Delay and Fall Time With 1F Load, 3.3V Switch
V C C D 0 = 3 .3 V
V C C D 0 = 3 .3 V
VCCD1
VCCD1
AV C C
AV C C
Figure 4. AVCC Propagation Delay and Rise Time With 147F Load, 3.3V Switch
Figure 5. AVCC Propagation Delay and Fall Time With 147F Load, 3.3V Switch
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Global Mixed-mode Technology Inc.
G571
VCCD0
VCCD0
VCCD1=5V
VCCD1=5V
AVCC
AVCC
Figure 6. AVCC Propagation Delay and Rise Time With 1F Load, 5V Switch
Figure 7. AVCC Propagation Delay and Fall Time With 1F Load, 5V Switch
VCCD0
VCCD0
VCCD1=5V
VCCD1=5V
AVCC
AVCC
Figure 8. AVCC Propagation Delay and Rise Time With 147F Load, 5V Switch
Figure 9. AVCC Propagation Delay and Fall Time With 147F Load, 5V Switch
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Global Mixed-mode Technology Inc.
G571
VPPD0
VPPD0
VPPD1=0V AVPP AVPP
VPPD1=0V
Figure 10. AVPP Propagation Delay and Rise Time With 1F Load, 12V Switch
Figure 11. AVPP Propagation Delay and Fall Time With 1F Load, 12V Switch
VPPD0
VPPD0
VPPD1=0V AVPP
VPPD1=0V AVPP
Figure 12. AVPP Propagation Delay and Rise Time With 147F Load, 12V Switch
Figure 13. AVPP Propagation Delay and Fall Time With 147F Load, 12V Switch
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Application Information
Overview PC Cards were initially introduced as a means to add EEPROM (flash memory) to portable computers with limited onboard memory. The idea of add-in cards quickly took hold; modems, wireless LANs, Global Positioning Satellite (GPS) systems, multimedia, and hard-disk versions were soon available. As the number of PC Card applications grew, the engineering community quickly recognized the need for a standard to ensure compatibility across platforms. To this end, the PCMCIA (Personal Computer Memory Card International Association) was established, comprised of members from leading computer, software, PC Card, and semiconductor manufactures. One key goal was to realize the "plug and play" concept, i.e. cards and hosts from different vendors should be compatible. PC Card Power Specification System compatibility also means power compatibility. The most current set of specifications (PC Card Standard) set forth by the PCMCIA committee states that power is to be transferred between the host and the card through eight of the 68 terminals of the PC Card connectors. This power interface consists of two VCC, two VPP, and four ground terminals. Multiple VCC and ground terminals minimize connector-terminal and line resistance. The two VPP terminals were originally specified as separate signals but are commonly tied together in the host to form a single node to minimize voltage losses. Card primary power is supplied through the VCC terminals; flash-memory programming and erase voltage is supplied through the VPP terminals. Designing for Voltage Regulation The current PCMCIA specification for output voltage regulation of the 5V output is 5% (250mV). In a typical PC power-system design, the power supply will have an output voltage regulation (VPS(reg)) of 2% (100mV). Also, a voltage drop from the power supply to the PC Card will result from resistive losses (VPCB) in the PCB traces and the PCMCIA connector. A typical design would limit the total of these resistive losses to less than 1% (50mV) of the output voltage. Therefore, the allowable voltage drop (VDS) for the G571 would be the PCMCIA voltage regulation less the power supply regula-tion and less the PCB and connector resistive drops: VDS = VO(reg)-VPS(reg)-VPCB Typically, this would leave 100mV for the allowable voltage drop across the G571. The voltage drop is the output current multiplied by the switch resistance of the G571. Therefore, the maximum output current that can be delivered to the PC Card in regulation is the allowable voltage drop across the G571 divided by the output switch resistance.
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G571
IOmax = VDS / RDS(on) The AVCC outputs deliver 1A continuous at 3.3V and 5.5V within regulation over the operating temperature range. Using the same equations, the PCMCIA specification for output voltage regulation of the 3.3V output is 300mV. Using the voltage drop percentages for power supply regulation (2%) and PCB resistive loss (1%), the allowable voltage drop for the 3.3V switch is 200mV. The 12V outputs (AVPP) of the G571 can deliver 150mA continuously. Overcurrent and overtemperature protection PC Cards are inherently subuect to damage from mishandling. Host systems require protection against short-circuited cards that could lead to power supply or PCB trace damage. Even systems sufficiently robust to withstand a short circuit would still undergo rapid battery discharge into the damaged PC Card, resulting in a sudden loss of system power. Most hosts include fuses for protection. The reliability of fused systems is poor, and requires troubleshooting and repair, usually by the manufacturer. When fuses are blown. The G571 uses sense FETs to check for overcurrent conditions in each of the AVCC and AVPP outputs.Unlike sense resistors or polyfuses, these FETs do not add to the series resistance of the switch; therefore voltage and power losses are reduced. Overcurrent sensing is applied to each output separately. When an overcurrent condition is detected, only the power output affected is limited; all other power outputs continue to function normally. The OC indicator, normally a ligic high, is a logic low when an overcurrent condition is detected providing for initiation of system diagnostics and/or sending a warning message to the user. During power up, the G571 controls the rise time of the AVCC and AVPP outputs and limits the current into a faulty card or connector. If a short circuit is applied after power is established (e.g., hot insertion of a bad card ),current is initially limited only by the impedance between the short and the power supply. In extreme cases, as much as 10A to 15A may flow into the short before the current limiting of the G571 engages. If the AVCC or AVPP outputs are driven below ground, the G571 may latch nondestructively in an off state, Cycling power will reestablish normal operation. Overcurrent limiting for the AVCC outputs is designed to activate if powered up into a short in the range of 0.8A to 2.2A, typically at about 1.5A. The AVPP outputs limit from 120mA to 400mA, typically around 200mA. The protection circuitry acts by linearly limiting the current passing through the switch rather than initiating a full shutdown of the supply. Shutdown occurs only during thermal limiting.
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Thermal limiting prevents destruction of the IC from overheating if the package power dissipation rating are exceeded. Thermal limiting disables power output until the device has cooled. 12V Supply Not Required Most PC Card switches use the externally supplied 12V to power gate drive and other chip functions, which require that power be present at all times. The G571 offers considerable power savings by using an internal charge pump to generate the required higher voltages from 5V input; Therefore, the external 12V supply can be disable except when needed for flash-memory functions, thereby extending battery lifetime. Do not ground the 12V switch inputs when the 12-V input is not used. Additional power savings are realized by the G571 during a software shutdown in which quiescent current drops to a maximum of 3A. 3.3V Low Voltage Mode The G571 will operates in a 3.3V low voltage mode when 3.3V is only available input voltage (VI(5V) = 0). This allows host and PC Cards to be operated in low-power 3.3V-only modes such as sleep modes or pager modes. Note that in these operation mode, the G571 will derive its bias current from the 3.3V input pin and only 3.3V can be delivered to the PC Card. Voltage Transitioning Requirement PC Cards are migrating from 5V to 3.3V to minimize power consumption, optimize board space, and increase logic speeds. The G571 meets all combinations of power delivery as currently defined in the PCMCIA standard. The latest protocol accommodates mixed 3.3V/5V systems by first powering the card with 5V, then polling it to determine its 3.3V compatibility. The PCMCIA specification requires that the capacitors on 3.3V-compatible cards be discharged to below
G571
0.8V before applying 3.3V power. This functions as a power reset and ensures that sensitive 3.3V circuitry is not subjected to any residual 5V charge. The G571 offer a selectable VCC and VPP ground state, in accordance with PCMCIA 3.3V/5V switching specifications. Output Ground Switches PC Card specification requires that VCC be discharged within 100 ms. PC Card resistance can not be relied on to provide a discharge path for voltages stored on PC Card capacitance because of possible high-impedance isolation by power-management schemes. Power Supply Considerations The G571 has multiple pins for each of its 3.3V, and 5V power inputs and for switched VCC outputs. Any individual pin can conduct the rated input or output current. Unless all pins are connected in parallel, the series resistance is significantly higher than that specified, resulting in increased voltage drops and lost power. it is recommended that all input and output power pins be paralleled for optimum operation. To increase the noise immunity of the G571, the power supply inputs should be bypassed with a 1F electrolytic or tantalum capacitor paralleled by a 0.047F to 0.1F ceramic capacitor. It is strongly recommended that the switched outputs be bypassed with a 0.1F or larger, ceramic capacitor; doing so improves the immunity of the G571 to electrostatic discharge (ESD). Care should be taken to minimize the inductance of PCB traces between the G571 and the load. High switching currents can produce large negative voltage transients, which forward biases substrate diodes, resulting in unpredictable performance. Similary, no pin should be taken below -0.3V.
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Global Mixed-mode Technology Inc.
G571
Card B 13 12 11 S4 17 51 VCC1 VCC2
G571
3.3V 3.3V 5V 5V 12V 3 4 5 6 S5 9 cs S6 10 18 52 VPP1 VPP2 S1 S2 S3 cs
See Note A Internal Current Monitor CPU 16 SHDN Thermal VPPD0 VPPD1 VCCD0 VCCD1 OC GND
Controller
15 14 1 2 8
7
Note A: MOSFET switch S6 has a back-gate diode from the source to the drain. Unused switch inputs should never be grounded. Figure 10. Internal Switching Matrix
G571 Control Logic
AVPP CONTROL SIGNALS VPPD0
0 0 1 1 x
SHDN
1 1 1 1 0
VPPD1
0 1 0 1 x
INTERNAL SWITCH SETTINGS S4 S5 S6
CLOSED OPEN OPEN OPEN OPEN OPEN CLOSED OPEN OPEN OPEN OPEN OPEN CLOSED OPEN OPEN
OUTPUT AVPP
0V AVCC* VPP(12V) Hi-Z Hi-Z
* Output depends on AVCC
AVCC CONTROL SIGNALS SHDN
1 1 1 1 0
VCCD1
0 0 1 1 x
VCCD0
0 1 0 1 x
INTERNAL SWITCH SETTINGS S1 S2 S3
CLOSED OPEN OPEN CLOSED OPEN OPEN CLOSED OPEN OPEN OPEN OPEN OPEN CLOSED OPEN OPEN
OUTPUT AVCC
0V 3.3V 5V 0V Hi-Z
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Package Information
G571
L1 R1 E1 E
L
D
c
A2 0.10MM C e b A1
A
Note: Dimension D does not include mold protrusions or gate burrs. Mold protrusions and gate burrs shall not exceed 0.006 inch per side. DIMENSION IN MM NOM.
--------1.75 0.30 0.15 0.65 BASIC 6.20 7.80 5.30 0.75 1.25 REF ----4
SYMBOL
A A1 A2 b c e D E E1 L L1 R1 JEDEC
MIN.
----0.05 1.65 0.22 0.09 5.90 7.40 5.00 0.55 0.09 0
MAX.
2.00 ----1.85 0.33 0.21 6.50 8.20 5.60 0.95 ----8
MIN.
----0.002 0.065 0.009 0.004 0.232 0.291 0.197 0.022 0.004 0 MO-150 (AC)
DIMENSION IN INCH NOM.
--------0.069 0.012 0.006 0.026 BASIC 0.244 0.307 0.209 0.030 0.049 REF ----4
MAX.
0.079 ----0.073 0.013 0.008 0.256 0.323 0.220 0.038 04 8
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